IP Registry
Growing registry with license detection. Dependency resolution and lock files. Reproducible across machines.
rr pkg search · add · update
T₀ // entry
v4.0.0 shipped to PyPI
The FPGA toolchain, already wired.
One CLI for dependencies, lint, simulation, synthesis, programming, and verification — across Vivado, Quartus, and Radiant. Real IP registry. Reproducible builds. No vendor lock-in.
$ pip install routertl
MIT licensed · Linux / WSL / Docker · Open source
registry · top namespaces
alex-forencich1 pkg
MIT
analog-devices346 pkgs
ADIBSD OR GPL-2.…
asicguy1 pkg
GPL-3.0-only
catalyst-neuromorphic1 pkg
Apache-2.0
ctu-fee1 pkg
MIT
enclustra3 pkgs
MIT
fpganinja14 pkgs
CERN-OHL-S-2.0
lxp321 pkg
MIT
registry.routertl.devbrowse all →
T₁ // capabilities
A complete FPGA workflow. Locally. In CI. With agents.
CI/CD & Pre-commit
Same flow locally and in CI. No drift. Configured in project.yml.
hooks.pre_commit.enabled: true
AI-Ready Workflows
Rules and schemas that AI agents can follow reliably. Pre-commit gates catch the rest.
rr testgen → scaffold → rr sim run → gate
T₂ // signal vs noise
Without RouteRTL vs. with.
Two channels. Same problem space. Drastically different traces.
topic
ch A · without
ch B · with
Dependency management
Copy-pasting source IPs between projects recursively.
Versioned modules (v4.4.1) via rr pkg add
Compilation & paths
Hardcoded absolute paths break synthesis unpredictably.
Topological sort auto-resolves identical compile orders.
Simulation tooling
Maintaining Makefile soup for Modelsim, Vivado, and GHDL.
One universal command: rr sim run
CI/CD & environments
Local development environment drifts slowly away from CI.
Same Docker-backed, pre-commit gated execution everywhere.
T₃ // agent-ready
agent_session.logreplaying
U
Add a UART module to the sensor hub and wire it to the main AXI bus.
A
Resolving dependencies, scaffolding tests…
$ rr pkg add open-logic/olo_base_uart
✓ extracted to vendor/open-logic/olo_base_uart
✓ updated project.yml
$ rr testgen olo_base_uart
✓ scaffolded tests/tb_uart.py
UART IP added; testbench boilerplate scaffolded. Wiring next.
Built so an agent can drive it. Without breaking your build.
Coding agents struggle with graphical EDA tools, complex Makefiles, and undocumented TCL paths. RouteRTL changes the equation with a declarative, deterministic interface the same agent can use as a senior engineer.
Declarative CLI rules
Agents can safely execute rr sim run or rr lint without worrying about vendor-specific toolchain gotchas.
Standardised YAML schemas
From project.yml to CSR memory maps, the entire configuration layer is machine-readable by design.
Scaffolding hooks
Agents use rr testgen and rr sim scaffold to bootstrap testbenches, reducing boilerplate and letting AI focus on verification logic.
T₄ // ships for agents
MCP server
rr exposes its tooling as a Model Context Protocol server. One command wires Claude Code, Cursor, Continue, or Zed into the rr surface — agents get direct access to rr_pkg_search, rr_doctor, rr_sim_*, rr_lint_*, rr_board_*, the rules engine, and the rest via .mcp.json.
$ rr mcp install
Claude Code skills
Procedure-grade skills ship with the SDK — ip-registry-maintenance, fpga-avmm-hang-diagnose, vivado-batch-mode, zynq7-sd-boot-bringup, and more. Claude discovers them automatically when rr is installed; the right one fires for the right problem.
$ pip install routertl
T₅ // zero to bitstream
Nine commands. One trace.
Each step is one CLI invocation. Works on Linux, WSL, Docker. Works with existing RTL projects — no rewrite required.
T0$pip installroutertl
T1$rr initsensor_hub
T2$rr pkg addopen-logic/olo_base_uart
T3$rr lint
T4$rr testgenolo_base_uart
T5$rr sim run
T6$rr synth run
T7$rr impl run
T8$rr bitstream run
what's in the box
- Register banks from YAML (VHDL · C · HTML)
- Built-in waveform viewer (RouteWave)
- VHDL / Verilog / SystemVerilog in one project
- Smart linting across the full hierarchy