2,000+ FPGA IP blocks.
Install — run — build. One CLI.
Real IP registry. Dependency resolution. Multi-vendor builds — fully automated.
A complete FPGA workflow.
Works locally, in CI, and with AI agents.
IP Registry
2,000+ blocks. Dependency resolution and lock files. Reproducible across machines.
rr pkg search / add / updateCI/CD & Pre-commit
Same flow locally and in CI. No drift. Configured in project.yml.
hooks.pre_commit.enabled: trueAI-Ready Workflows
Rules and schemas that AI agents can follow reliably. Pre-commit gates catch the rest.
rr test-gen → scaffold → rr sim → gateWhat You Get Out of the Box
Your toolchain does the heavy lifting. We handle the rest.
Vendor toolchains are essential, but the manual scripting required to connect them shouldn't be. RouteRTL fills the massive gap among them, providing the exact same CLI for dependencies, linting, and compile orders across Vivado, Quartus, Radiant, and more.
In practice, this leads to:
The difference is night and day
A look at standard FPGA engineering compared to the RouteRTL workflow.
Dependency Management
Copy-pasting source IPs between projects recursively.
Dependency Management
Versioned modules (v4.4.1) via rr pkg add.
Compilation & Paths
Hardcoded absolute paths break synthesis unpredictably.
Compilation & Paths
Topological sort auto-resolves identical compile orders.
Simulation Tooling
Maintaining Makefile soup for Modelsim, Vivado, and GHDL.
Simulation Tooling
One universal command: rr sim switches engines instantly.
CI/CD & Environments
Local development environment drifts slowly away from CI.
CI/CD & Environments
Same Docker-backed, pre-commit gated execution everywhere.
Why it matters
Day-one productivity
Clone, init, simulate — no tribal knowledge needed
Same result on every machine
Visible dependency graph
Know what depends on what before you build
CI from the start
Docker environments and pre-commit gates included
The first EDA flow
built for agents
AI coding agents struggle with graphical EDA tools, complex Makefiles, and undocumented TCL paths. RouteRTL changes the equation by providing a declarative, deterministic interface.
Declarative CLI Rules
Agents can safely execute `rr sim` or `rr lint` without worrying about vendor-specific toolchain gotchas.
Standardized YAML Schemas
From `project.yml` to CSR memory maps, the entire configuration layer is machine-readable by design.
Scaffolding Hooks
Agents can use `rr test-gen` to bootstrap testbenches, reducing boilerplate and letting AI focus on logic logic verification.
The RouteRTL Ecosystem
See the signals,
fast.
Say goodbye to clunky Java GUIs. RouteRTL includes RouteWave, a next-gen, GPU-accelerated waveform viewer that opens instantly from your terminal.
The full flow
From zero to bitstream
Each step is one command. rr lint works immediately after install. rr testgen scaffolds the Cocotb testbench — fill in the test logic yourself or with AI. Then simulate and synthesise.
Works on Linux, WSL, and Docker. Works with existing RTL projects — no rewrite required.